A 4.5 Gb/s/pin transceiver capable of eliminating the inter-symbol interference (ISI) and far-end crosstalk (FEXT) in a hybrid scheme with low power and small area for next-generation high-bandwidth memory (HBM) interfaces is presented. Built around the combination of two ISI and FEXT equalization topologies, the transmitter (TX) energy efficiently reduces data-dependent jitter (DDJ) and crosstalk-induced jitter (CIJ) by using the compensation signal generated from edge detectors (ED) to ensure the sampling margin. The prototype transceiver, implemented using a 28-nm complementary metal-oxide semiconductor (CMOS) process, operates over a 3-mm mimicked silicon interposer channel with 21.2-dB loss. It achieves a data rate per density of 9 Gb/s/μm at a bit error rate (BER) < 10–12 with 0.23 unit interval (UI) eye width for pseudorandom binary sequence (PRBS)15 data while consuming only 1.46 pJ/bit.
|Number of pages||3|
|Publication status||Published - 2022 May|
ASJC Scopus subject areas
- Electrical and Electronic Engineering