A 5-bit 500-MS/s flash ADC using time-domain comparison

Young Jae Min, Hoon Ki Kim, Chulwoo Kim, Soo Won Kim, Gil Su Kim

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.

Original languageEnglish
Article number1240023
JournalJournal of Circuits, Systems and Computers
Issue number8
Publication statusPublished - 2012 Dec


  • Analog-to-digital converter
  • flash converter
  • time-domain comparison
  • voltage-to-time converter

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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