A 5-bit 500-MS/s flash ADC using time-domain comparison

Young Jae Min, Hoon Ki Kim, Chulwoo Kim, Soo-Won Kim, Gil Su Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.

Original languageEnglish
Article number1240023
JournalJournal of Circuits, Systems and Computers
Volume21
Issue number8
DOIs
Publication statusPublished - 2012 Dec 1

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Ladders
Reusability
Electric potential
Resistors
Masks
Electric power utilization

Keywords

  • Analog-to-digital converter
  • flash converter
  • time-domain comparison
  • voltage-to-time converter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

A 5-bit 500-MS/s flash ADC using time-domain comparison. / Min, Young Jae; Kim, Hoon Ki; Kim, Chulwoo; Kim, Soo-Won; Kim, Gil Su.

In: Journal of Circuits, Systems and Computers, Vol. 21, No. 8, 1240023, 01.12.2012.

Research output: Contribution to journalArticle

@article{e63e4c473eb24f4c82be399f3cb9875e,
title = "A 5-bit 500-MS/s flash ADC using time-domain comparison",
abstract = "A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.",
keywords = "Analog-to-digital converter, flash converter, time-domain comparison, voltage-to-time converter",
author = "Min, {Young Jae} and Kim, {Hoon Ki} and Chulwoo Kim and Soo-Won Kim and Kim, {Gil Su}",
year = "2012",
month = "12",
day = "1",
doi = "10.1142/S0218126612400233",
language = "English",
volume = "21",
journal = "Journal of Circuits, Systems and Computers",
issn = "0218-1266",
publisher = "World Scientific Publishing Co. Pte Ltd",
number = "8",

}

TY - JOUR

T1 - A 5-bit 500-MS/s flash ADC using time-domain comparison

AU - Min, Young Jae

AU - Kim, Hoon Ki

AU - Kim, Chulwoo

AU - Kim, Soo-Won

AU - Kim, Gil Su

PY - 2012/12/1

Y1 - 2012/12/1

N2 - A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.

AB - A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.

KW - Analog-to-digital converter

KW - flash converter

KW - time-domain comparison

KW - voltage-to-time converter

UR - http://www.scopus.com/inward/record.url?scp=84874667109&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874667109&partnerID=8YFLogxK

U2 - 10.1142/S0218126612400233

DO - 10.1142/S0218126612400233

M3 - Article

AN - SCOPUS:84874667109

VL - 21

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

SN - 0218-1266

IS - 8

M1 - 1240023

ER -