A 5-bit 500-MS/s time-domain flash ADC in 0.18-μm CMOS

Young Jae Min, Ammar Abdullah, Hoon Ki Kim, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18μm CMOS technology and occupies 0.132mm 2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8mW with a 1.8-V supply voltage.

Original languageEnglish
Title of host publication2011 International Symposium on Integrated Circuits, ISIC 2011
Pages336-339
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore
Duration: 2011 Dec 122011 Dec 14

Other

Other2011 International Symposium on Integrated Circuits, ISIC 2011
CountrySingapore
CitySingaporeSingapore
Period11/12/1211/12/14

Fingerprint

Ladders
Reusability
Electric potential
Resistors
Masks
Electric power utilization

Keywords

  • Analog-to-digital converter
  • Flash converter
  • Time-domain comparison
  • Voltage-to-time converter

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Min, Y. J., Abdullah, A., Kim, H. K., & Kim, S-W. (2011). A 5-bit 500-MS/s time-domain flash ADC in 0.18-μm CMOS. In 2011 International Symposium on Integrated Circuits, ISIC 2011 (pp. 336-339). [6131965] https://doi.org/10.1109/ISICir.2011.6131965

A 5-bit 500-MS/s time-domain flash ADC in 0.18-μm CMOS. / Min, Young Jae; Abdullah, Ammar; Kim, Hoon Ki; Kim, Soo-Won.

2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 336-339 6131965.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Min, YJ, Abdullah, A, Kim, HK & Kim, S-W 2011, A 5-bit 500-MS/s time-domain flash ADC in 0.18-μm CMOS. in 2011 International Symposium on Integrated Circuits, ISIC 2011., 6131965, pp. 336-339, 2011 International Symposium on Integrated Circuits, ISIC 2011, SingaporeSingapore, Singapore, 11/12/12. https://doi.org/10.1109/ISICir.2011.6131965
Min YJ, Abdullah A, Kim HK, Kim S-W. A 5-bit 500-MS/s time-domain flash ADC in 0.18-μm CMOS. In 2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 336-339. 6131965 https://doi.org/10.1109/ISICir.2011.6131965
Min, Young Jae ; Abdullah, Ammar ; Kim, Hoon Ki ; Kim, Soo-Won. / A 5-bit 500-MS/s time-domain flash ADC in 0.18-μm CMOS. 2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. pp. 336-339
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