This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio (δ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a -104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2017 Oct|
- spread-spectrum clock generator (SSCG)
- subsampling phase-locked loop (SSPLL)
ASJC Scopus subject areas
- Electrical and Electronic Engineering