A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation

Sang Geun Bae, Gyungmin Kim, Chulwoo Kim

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio (δ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a -104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.

Original languageEnglish
Article number7733152
Pages (from-to)1132-1136
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume64
Issue number10
DOIs
Publication statusPublished - 2017 Oct 1

Fingerprint

Phase locked loops
Clocks
Phase noise
Variable frequency oscillators
Signal interference
Jitter
Modulation
Calibration
Electric potential
Temperature

Keywords

  • Auto-calibration
  • spread-spectrum clock generator (SSCG)
  • subsampling phase-locked loop (SSPLL)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation. / Bae, Sang Geun; Kim, Gyungmin; Kim, Chulwoo.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 10, 7733152, 01.10.2017, p. 1132-1136.

Research output: Contribution to journalArticle

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