A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13μm CMOS

Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Abstract

An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10 12 at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm 2 using 0.13μm CMOS process.

Original languageEnglish
Pages1959-1962
Number of pages4
DOIs
Publication statusPublished - 2012 Sep 28
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 2012 May 202012 May 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period12/5/2012/5/23

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hwang, S., Jung, I., Song, J., & Kim, C. (2012). A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13μm CMOS. 1959-1962. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271659