Abstract
This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 Vpp-diff input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27-mm2 area.
| Original language | English |
|---|---|
| Article number | 6977959 |
| Pages (from-to) | 2371-2383 |
| Number of pages | 13 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 23 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - 2015 Nov 1 |
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Keywords
- Analog-to-digital converter (ADC)
- calibration
- input folding
- resistive digital-to-analog converter (RDAC)
- successive approximation register (SAR)
- Time-interleaving (TI)
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
Cite this
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter. / Lee, Hokyu; Aurangozeb; Park, Sejin; Kim, Jintae; Kim, Chulwoo.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 11, 6977959, 01.11.2015, p. 2371-2383.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter
AU - Lee, Hokyu
AU - Aurangozeb,
AU - Park, Sejin
AU - Kim, Jintae
AU - Kim, Chulwoo
PY - 2015/11/1
Y1 - 2015/11/1
N2 - This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 Vpp-diff input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27-mm2 area.
AB - This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 Vpp-diff input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27-mm2 area.
KW - Analog-to-digital converter (ADC)
KW - calibration
KW - input folding
KW - resistive digital-to-analog converter (RDAC)
KW - successive approximation register (SAR)
KW - Time-interleaving (TI)
UR - http://www.scopus.com/inward/record.url?scp=84914820690&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84914820690&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2014.2372033
DO - 10.1109/TVLSI.2014.2372033
M3 - Article
VL - 23
SP - 2371
EP - 2383
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 11
M1 - 6977959
ER -