A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter

Hokyu Lee, Aurangozeb, Sejin Park, Jintae Kim, Chulwoo Kim

Research output: Contribution to journalArticle

7 Citations (Scopus)


This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 Vpp-diff input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27-mm2 area.

Original languageEnglish
Article number6977959
Pages (from-to)2371-2383
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number11
Publication statusPublished - 2015 Nov 1



  • Analog-to-digital converter (ADC)
  • calibration
  • input folding
  • resistive digital-to-analog converter (RDAC)
  • successive approximation register (SAR)
  • Time-interleaving (TI)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

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