Abstract
This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18GHz bandwidth with a nominal 17-25dB conversion gain, worst-case -15dBm IIP3, and worst-case -24.5dBm ICP1dB.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2008 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2008 |
| Pages | 343-346 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2008 |
| Event | 2008 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2008 - Atlanta, GA, United States Duration: 2008 Jun 15 → 2008 Jun 17 |
Publication series
| Name | Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium |
|---|---|
| ISSN (Print) | 1529-2517 |
Other
| Other | 2008 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2008 |
|---|---|
| Country | United States |
| City | Atlanta, GA |
| Period | 08/6/15 → 08/6/17 |
Keywords
- Concurrent
- Dual-band
- Low-noise amplifier
- Phased array
- Receiver architecture
ASJC Scopus subject areas
- Engineering(all)
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Cite this
Wang, Y. J., Jeon, S., Babakhani, A., & Hajimiri, A. (2008). A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS. In Proceedings of the 2008 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2008 (pp. 343-346). [4561450] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2008.4561450