A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge

Kyeongho Lee, Woong Choi, Jongsun Park

Research output: Contribution to journalArticlepeer-review

Abstract

This article presents an adaptive match-line (ML) discharge scheme for low-power, high-performance, and compact ternary content addressable memory (TCAM). In the proposed TCAM, the transposed cell topology enables the selectively controlled ML pull-down path and compact array area. By employing the adaptive ML discharge and ML boosting scheme, unnecessary ML discharge and redundant search-line (SL) switching are eliminated for low-cost TCAM search operation. In order to minimize ML voltage swing at a wide voltage range, a timing calibration scheme is also adopted in the proposed TCAM. A 128 x 64 test chip implemented with 65-nm CMOS technology shows that the proposed adaptive ML discharge improves up to 69% of search delay and saves 37% of search energy compared with the conventional approach at 1.1 V, 100 MHz. The measurement result shows energy efficiency of 0.6 fJ/bit/search and 8% improvement of figure-of-merit (FoM) (energy/bit/search) compared with the state-of-the-art works.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
DOIs
Publication statusAccepted/In press - 2020

Keywords

  • Adaptive sensing
  • Boosting
  • Computer architecture
  • content addressable memory (CAM)
  • Discharges (electric)
  • memory
  • Microprocessors
  • Power demand
  • reference voltage
  • sensing margin
  • Sensors
  • Switches
  • ternary CAM (TCAM).

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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