Abstract
This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.
| Original language | English |
|---|---|
| Article number | 5226752 |
| Pages (from-to) | 2437-2451 |
| Number of pages | 15 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 44 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 2009 Sep 1 |
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Keywords
- Delay-locked loop (DLL)
- Duty cycle corrector (DCC)
- Fine code generator
- Range doubler
- Time-to-digital converter (TDC)
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A 7 ps jitter 0.053 mm2 fast lock all-digital DLL with a wide range and high resolution DCC. / Shin, Dongsuk; Song, Janghoon; Chae, Hyunsoo; Kim, Chulwoo.
In: IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, 5226752, 01.09.2009, p. 2437-2451.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 7 ps jitter 0.053 mm2 fast lock all-digital DLL with a wide range and high resolution DCC
AU - Shin, Dongsuk
AU - Song, Janghoon
AU - Chae, Hyunsoo
AU - Kim, Chulwoo
PY - 2009/9/1
Y1 - 2009/9/1
N2 - This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.
AB - This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.
KW - Delay-locked loop (DLL)
KW - Duty cycle corrector (DCC)
KW - Fine code generator
KW - Range doubler
KW - Time-to-digital converter (TDC)
UR - http://www.scopus.com/inward/record.url?scp=70249134908&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70249134908&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2009.2021447
DO - 10.1109/JSSC.2009.2021447
M3 - Article
AN - SCOPUS:70249134908
VL - 44
SP - 2437
EP - 2451
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 9
M1 - 5226752
ER -