A 7 ps jitter 0.053 mm2 fast lock all-digital DLL with a wide range and high resolution DCC

Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Chulwoo Kim

Research output: Contribution to journalArticle

56 Citations (Scopus)

Abstract

This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.

Original languageEnglish
Article number5226752
Pages (from-to)2437-2451
Number of pages15
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number9
DOIs
Publication statusPublished - 2009 Sep 1

Keywords

  • Delay-locked loop (DLL)
  • Duty cycle corrector (DCC)
  • Fine code generator
  • Range doubler
  • Time-to-digital converter (TDC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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