TY - JOUR
T1 - A 7.5-Gb/s Referenceless transceiver with adaptive equalization and bandwidth-shifting technique for ultrahigh-definition television in a 0.13-μm CMOS Process
AU - Song, Junyoung
AU - Hwang, Sewook
AU - Lee, Hyun Woo
AU - Kim, Chulwoo
PY - 2014/11/1
Y1 - 2014/11/1
N2 - This brief proposes a 7.5-Gb/s transceiver with adaptive equalization and a bandwidth (BW)-shifting technique for ultrahigh-definition television. By applying dynamic preemphasis calibration and a BW-shifting phase-locked loop/clock and data recovery, the measured jitter of the output data with a 16.88-dB loss cable and clock are enhanced by 49.9% and 40%, respectively. In addition, a data-width-comparison-based adaptive equalizer with a self-adjusting reference voltage is proposed. With a 3.37-MHz sinusoidal jitter, the measured jitter tolerance of the proposed receiver is improved from 1.07UI to 2.97UI. The transmitter and the receiver consume 10.08 and 9.28 mW/Gb/s at 7.5 Gb/s, respectively, and occupy 0.14 and 0.15 mm2, respectively, using a 0.13- μm complementary metal-oxide-semiconductor process.
AB - This brief proposes a 7.5-Gb/s transceiver with adaptive equalization and a bandwidth (BW)-shifting technique for ultrahigh-definition television. By applying dynamic preemphasis calibration and a BW-shifting phase-locked loop/clock and data recovery, the measured jitter of the output data with a 16.88-dB loss cable and clock are enhanced by 49.9% and 40%, respectively. In addition, a data-width-comparison-based adaptive equalizer with a self-adjusting reference voltage is proposed. With a 3.37-MHz sinusoidal jitter, the measured jitter tolerance of the proposed receiver is improved from 1.07UI to 2.97UI. The transmitter and the receiver consume 10.08 and 9.28 mW/Gb/s at 7.5 Gb/s, respectively, and occupy 0.14 and 0.15 mm2, respectively, using a 0.13- μm complementary metal-oxide-semiconductor process.
KW - Adaptive equalizer
KW - bandwidth (BW) control
KW - phase-locked loop (PLL)
KW - preemphasis
KW - transmitter (TX)
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U2 - 10.1109/TCSII.2014.2350294
DO - 10.1109/TCSII.2014.2350294
M3 - Article
AN - SCOPUS:84910096458
VL - 61
SP - 865
EP - 869
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 11
M1 - 6881622
ER -