A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

Hyun Woo Lee, Yong Hoon Kim, Won Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young Jung Choi, Byong Tae Chung, Joong Sik Kih

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages3861-3864
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: 2010 May 302010 Jun 2

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period10/5/3010/6/2

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Lee, H. W., Kim, Y. H., Yun, W. J., Park, E. Y., Lee, K. Y., Kim, J., Kim, K. H., Jung, J. H., Kim, K. W., Rye, N. G., Kim, K. W., Chun, J. H., Kim, C., Choi, Y. J., Chung, B. T., & Kih, J. S. (2010). A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3861-3864). [5537703] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537703