A 7ps-jitter 0.053mm2 fast-lock ADDLL with wide-range and high-resolution all-digital DCC

Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan Weon Kim, Young Jung Choi, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

An ADDLL is designed to achieve low jitter, fast lock time and nearly 50% duty cycle with an open-loop duty-cycle corrector. The ADDLL operates over a frequency range from 440MHz to 1.5GHz with 15 cycles of maximum lock-in time and occupies 0.053mm2 in 0.18μm 1.8V CMOS. The peak-to-peak jitter is 7ps at 1.5GHz and the power consumption is 43mW.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
Publication statusPublished - 2007 Sep 27
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 2007 Feb 112007 Feb 15

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period07/2/1107/2/15

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Shin, D., Song, J., Chae, H., Kim, K. W., Choi, Y. J., & Kim, C. (2007). A 7ps-jitter 0.053mm2 fast-lock ADDLL with wide-range and high-resolution all-digital DCC. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [4242326] https://doi.org/10.1109/ISSCC.2007.373355