A 7ps-jitter 0.053mm2 fast-lock ADDLL with wide-range and high-resolution all-digital DCC

Dongsuk Shin; Janghoon Song; Hyunsoo Chae; Kwan Weon Kim; Young Jung Choi; Chulwoo Kim

doi:10.1109/ISSCC.2007.373355

A 7ps-jitter 0.053mm² fast-lock ADDLL with wide-range and high-resolution all-digital DCC

Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan Weon Kim, Young Jung Choi, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

An ADDLL is designed to achieve low jitter, fast lock time and nearly 50% duty cycle with an open-loop duty-cycle corrector. The ADDLL operates over a frequency range from 440MHz to 1.5GHz with 15 cycles of maximum lock-in time and occupies 0.053mm² in 0.18μm 1.8V CMOS. The peak-to-peak jitter is 7ps at 1.5GHz and the power consumption is 43mW.

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	184-186
Number of pages	3
ISBN (Print)	1424408539, 9781424408535
DOIs	https://doi.org/10.1109/ISSCC.2007.373355
Publication status	Published - 2007
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: 2007 Feb 11 → 2007 Feb 15

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/Territory	United States
City	San Francisco, CA
Period	07/2/11 → 07/2/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2007.373355

Cite this

Shin, D., Song, J., Chae, H., Kim, K. W., Choi, Y. J., & Kim, C. (2007). A 7ps-jitter 0.053mm² fast-lock ADDLL with wide-range and high-resolution all-digital DCC. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 184-186). [4242326] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373355

A 7ps-jitter 0.053mm² fast-lock ADDLL with wide-range and high-resolution all-digital DCC. / Shin, Dongsuk; Song, Janghoon; Chae, Hyunsoo et al.

2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 184-186 4242326 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shin, D, Song, J, Chae, H, Kim, KW, Choi, YJ & Kim, C 2007, A 7ps-jitter 0.053mm² fast-lock ADDLL with wide-range and high-resolution all-digital DCC. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242326, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 184-186, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373355

Shin D, Song J, Chae H, Kim KW, Choi YJ, Kim C. A 7ps-jitter 0.053mm² fast-lock ADDLL with wide-range and high-resolution all-digital DCC. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 184-186. 4242326. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373355

Shin, Dongsuk ; Song, Janghoon ; Chae, Hyunsoo et al. / A 7ps-jitter 0.053mm² fast-lock ADDLL with wide-range and high-resolution all-digital DCC. 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 184-186 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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