A 9 Gb/s/ch Transceiver with Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces

Junyoung Song, Yongtae Kim, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10-12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 psRMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.

Original languageEnglish
Article number8628259
Pages (from-to)1982-1986
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume66
Issue number12
DOIs
Publication statusPublished - 2019 Dec

Keywords

  • data-embedded clock signaling
  • DRAM
  • graphics DRAM
  • memory interface
  • multi-level signaling
  • reference-less interface
  • transceiver

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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