TY - GEN
T1 - A 90-GHz High DC-To-RF Efficiency VCO with Multi-Way Transformers in 65-nm CMOS
AU - Yoo, Junghwan
AU - Son, Heekang
AU - Kim, Jungsoo
AU - Kim, Doyoon
AU - Rieh, Jae Sung
N1 - Funding Information:
This work was supported by Samsung Electronics Co., Ltd. and Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. 2016-0-00185).
Publisher Copyright:
© 2020 IEEE.
PY - 2020/9
Y1 - 2020/9
N2 - This paper presents a high efficiency gate inductive feedback Colpitts Voltage Controlled Oscillator (VCO) operating near 90 GHz. It includes multi-way transformers at the load, which helps to enhance the DC-To-RF efficiency with boosted impedance and extended voltage swing through drain-buffer and drain-source magnetic couplings. The proposed VCO is fabricated in a 65-nm CMOS process, and showed an oscillation frequency tuning range of 87.5-92.0 GHz (4.5 GHz). Over the frequency range, the output power and the dc power consumption exhibited values of-2.8-1.7 dBm and 6-22.5 mW, respectively. The peak DC-To-RF efficiency was 9.4 %, and the corresponding phase noise was-107.4 dBc/Hz at 10-MHz offset. The lowest phase noise at the optimum bias condition was-116.7 dB/Hz at 10-MHz offset. The chip size is 400 300 μm2 excluding DC and RF pads.
AB - This paper presents a high efficiency gate inductive feedback Colpitts Voltage Controlled Oscillator (VCO) operating near 90 GHz. It includes multi-way transformers at the load, which helps to enhance the DC-To-RF efficiency with boosted impedance and extended voltage swing through drain-buffer and drain-source magnetic couplings. The proposed VCO is fabricated in a 65-nm CMOS process, and showed an oscillation frequency tuning range of 87.5-92.0 GHz (4.5 GHz). Over the frequency range, the output power and the dc power consumption exhibited values of-2.8-1.7 dBm and 6-22.5 mW, respectively. The peak DC-To-RF efficiency was 9.4 %, and the corresponding phase noise was-107.4 dBc/Hz at 10-MHz offset. The lowest phase noise at the optimum bias condition was-116.7 dB/Hz at 10-MHz offset. The chip size is 400 300 μm2 excluding DC and RF pads.
KW - CMOS technology
KW - DC-To-RF efficiency
KW - phase noise
KW - voltage-controlled oscillators
UR - http://www.scopus.com/inward/record.url?scp=85096511018&partnerID=8YFLogxK
U2 - 10.1109/RFIT49453.2020.9226213
DO - 10.1109/RFIT49453.2020.9226213
M3 - Conference contribution
AN - SCOPUS:85096511018
T3 - 2020 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2020
SP - 25
EP - 27
BT - 2020 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2020
Y2 - 2 September 2020 through 4 September 2020
ER -