TY - GEN
T1 - A 97.9% Peak Efficiency 9 v Output Three-Switch Hybrid Buck-Boost Power Stage Using 5 v CMOS
AU - Kim, Hyunjin
AU - Park, Taehyeong
AU - Kim, Chulwoo
N1 - Funding Information:
This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (MIST) under Grant 2022R1A2C3012245.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - this paper, a three-switch hybrid buck-boost DC-DC converter is presented to achieve a high power conversion efficiency (PCE) with a high power density. The proposed power stage employs one inductor and one flying capacitor with three 5 V CMOS switches, generating a minimum of 1 V to a maximum output voltage of 9 V. In addition, the power switches use a constant gate-source voltage for both step-down and step-up turn-on operations, enhancing the converter to achieve a (a) PCE of over 85.6% at an output load current (I{\mathrm{OUT}}) of 1 A. The converter is implemented using a conventional voltage-mode type-III compensation circuit. In addition, the gate drivers use 5 V CMOS devices to drive the power switches with low fabrication costs. In this study, the prototype chip was designed and simulated in a 180 nm BCD process, and the peak efficiency was simulated to be 96.9% and 97.9% in the buck and boost modes, respectively, with a maximum I{\mathrm{OUT}} of 2 A.
AB - this paper, a three-switch hybrid buck-boost DC-DC converter is presented to achieve a high power conversion efficiency (PCE) with a high power density. The proposed power stage employs one inductor and one flying capacitor with three 5 V CMOS switches, generating a minimum of 1 V to a maximum output voltage of 9 V. In addition, the power switches use a constant gate-source voltage for both step-down and step-up turn-on operations, enhancing the converter to achieve a (a) PCE of over 85.6% at an output load current (I{\mathrm{OUT}}) of 1 A. The converter is implemented using a conventional voltage-mode type-III compensation circuit. In addition, the gate drivers use 5 V CMOS devices to drive the power switches with low fabrication costs. In this study, the prototype chip was designed and simulated in a 180 nm BCD process, and the peak efficiency was simulated to be 96.9% and 97.9% in the buck and boost modes, respectively, with a maximum I{\mathrm{OUT}} of 2 A.
KW - DC-DC converter
KW - RMS inductor current reduction
KW - hybrid buck-boost converter
KW - three-switch converter
UR - http://www.scopus.com/inward/record.url?scp=85137451854&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS54063.2022.9859439
DO - 10.1109/MWSCAS54063.2022.9859439
M3 - Conference contribution
AN - SCOPUS:85137451854
T3 - Midwest Symposium on Circuits and Systems
BT - MWSCAS 2022 - 65th IEEE International Midwest Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022
Y2 - 7 August 2022 through 10 August 2022
ER -