A Δ∑-Modulator based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for PLL Loop Bandwidth

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip (SoC) without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the PLL loop bandwidth (fLBW). This paper proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292mm2.