A Δ∑-Modulator based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for PLL Loop Bandwidth

Sang Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip (SoC) without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the PLL loop bandwidth (fLBW). This paper proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292mm2.

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
DOIs
Publication statusAccepted/In press - 2018 Jun 11

Fingerprint

Signal interference
Phase locked loops
Modulators
Clocks
Calibration
Bandwidth
Jitter
Shielding
Electric power utilization
Compensation and Redress
Costs

Keywords

  • Calibration
  • Detectors
  • digital compensation.
  • Electromagnetic interference
  • EMI reduction
  • Frequency modulation
  • Generators
  • Phase locked loops
  • PLL
  • spread-spectrum clock
  • SSCG

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

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title = "A Δ∑-Modulator based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for PLL Loop Bandwidth",
abstract = "A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip (SoC) without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the PLL loop bandwidth (fLBW). This paper proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292mm2.",
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author = "Bae, {Sang Geun} and Sewook Hwang and Junyoung Song and Yeonho Lee and Chulwoo Kim",
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AU - Bae, Sang Geun

AU - Hwang, Sewook

AU - Song, Junyoung

AU - Lee, Yeonho

AU - Kim, Chulwoo

PY - 2018/6/11

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N2 - A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip (SoC) without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the PLL loop bandwidth (fLBW). This paper proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292mm2.

AB - A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip (SoC) without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the PLL loop bandwidth (fLBW). This paper proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292mm2.

KW - Calibration

KW - Detectors

KW - digital compensation.

KW - Electromagnetic interference

KW - EMI reduction

KW - Frequency modulation

KW - Generators

KW - Phase locked loops

KW - PLL

KW - spread-spectrum clock

KW - SSCG

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