A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance

Sungsoo Cheon, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference, ISOCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages294-295
Number of pages2
ISBN (Electronic)9781728183312
DOIs
Publication statusPublished - 2020 Oct 21
Event17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of
Duration: 2020 Oct 212020 Oct 24

Publication series

NameProceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference17th International System-on-Chip Design Conference, ISOCC 2020
Country/TerritoryKorea, Republic of
CityYeosu
Period20/10/2120/10/24

Keywords

  • Assist Technique
  • BL Computation
  • Read Disturb
  • SRAM

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture

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