A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance

Sungsoo Cheon; Jongsun Park

doi:10.1109/ISOCC50952.2020.9333096

A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance

Sungsoo Cheon, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	294-295
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333096
Publication status	Published - 2020 Oct 21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

Keywords

Assist Technique
BL Computation
Read Disturb
SRAM

ASJC Scopus subject areas

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC50952.2020.9333096

Cite this

Cheon, S., & Park, J. (2020). A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 294-295). [9333096] (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9333096

A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance. / Cheon, Sungsoo; Park, Jongsun.

Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 294-295 9333096 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cheon, S & Park, J 2020, A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333096, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 294-295, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9333096

@inproceedings{fa3d0ea70b1d4a559d736321c16d1abc,

title = "A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance",

abstract = "SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture. ",

keywords = "Assist Technique, BL Computation, Read Disturb, SRAM",

author = "Sungsoo Cheon and Jongsun Park",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

year = "2020",

month = oct,

day = "21",

doi = "10.1109/ISOCC50952.2020.9333096",

language = "English",

series = "Proceedings - International SoC Design Conference, ISOCC 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "294--295",

booktitle = "Proceedings - International SoC Design Conference, ISOCC 2020",

}

TY - GEN

T1 - A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance

AU - Cheon, Sungsoo

AU - Park, Jongsun

PY - 2020/10/21

Y1 - 2020/10/21

N2 - SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.

AB - SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.

KW - Assist Technique

KW - BL Computation

KW - Read Disturb

KW - SRAM

UR - http://www.scopus.com/inward/record.url?scp=85100703667&partnerID=8YFLogxK

U2 - 10.1109/ISOCC50952.2020.9333096

DO - 10.1109/ISOCC50952.2020.9333096

M3 - Conference contribution

AN - SCOPUS:85100703667

T3 - Proceedings - International SoC Design Conference, ISOCC 2020

SP - 294

EP - 295

BT - Proceedings - International SoC Design Conference, ISOCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International System-on-Chip Design Conference, ISOCC 2020

Y2 - 21 October 2020 through 24 October 2020

ER -

A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance

Abstract

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Conference

Keywords

ASJC Scopus subject areas

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