TY - GEN
T1 - A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance
AU - Cheon, Sungsoo
AU - Park, Jongsun
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.
AB - SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.
KW - Assist Technique
KW - BL Computation
KW - Read Disturb
KW - SRAM
UR - http://www.scopus.com/inward/record.url?scp=85100703667&partnerID=8YFLogxK
U2 - 10.1109/ISOCC50952.2020.9333096
DO - 10.1109/ISOCC50952.2020.9333096
M3 - Conference contribution
AN - SCOPUS:85100703667
T3 - Proceedings - International SoC Design Conference, ISOCC 2020
SP - 294
EP - 295
BT - Proceedings - International SoC Design Conference, ISOCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International System-on-Chip Design Conference, ISOCC 2020
Y2 - 21 October 2020 through 24 October 2020
ER -