An 8-bit cascaded-dividing DAC that can operate at a low power supply voltage is proposed. Occupying less than one eleventh of the chip area of a conventional binary-weighted DAC with an equivalent resolution, the proposed DAC features a low operation voltage of 2 V with a good DNL and INL of less than 0.15 LSB. The proposed DAC is expected to be adequate for current-driving AMOLED drivers that have very demanding requirements of a narrow channel pitch as well as high linearity and resolution for the data channel DACs.
|Number of pages||3|
|Journal||Digest of Technical Papers - SID International Symposium|
|Publication status||Published - 2007 Aug 22|
|Event||2007 SID International Symposium - Long Beach, CA, United States|
Duration: 2007 May 23 → 2007 May 25
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