A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference

Joonhyung Kim, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

SRAM-based In-Memory-Computing (IMC) for processing multiply-Accumulate (MAC) operations is one of the promising techniques to overcome von-Neumann Bottleneck. The SRAM-based IMC generally requires multi-bit input activation to achieve a high inference accuracy. In this paper, a charge-sharing based 10T SRAM IMC architecture is proposed which can process multibit inputs on cell array by employing bit-line parasitic capacitances without Digital to Analog Converter (DAC). The proposed DAC-less multi-bit IMC can efficiently reduce computing energy without latency overhead. The hardware implementation with 28nm CMOS process shows that the proposed SRAM based IMC macro achieves 10.1TOPS/W with 7ns inference time at 1V and 91.4% CIFAR-10 inference accuracy.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2021, ISOCC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages89-90
Number of pages2
ISBN (Electronic)9781665401746
DOIs
Publication statusPublished - 2021
Event18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of
Duration: 2021 Oct 62021 Oct 9

Publication series

NameProceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference18th International System-on-Chip Design Conference, ISOCC 2021
Country/TerritoryKorea, Republic of
CityJeju Island
Period21/10/621/10/9

Keywords

  • Deep Neural Network (DNN)
  • In-Memory Computing(IMC)
  • Multiply-Accumulate (MAC)
  • SRAM

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Information Systems
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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