A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling

Jin Han Kim, Young Ho Kwak, Seok Ryung Yoon, Moo Young Kim, Soo-Won Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6ps pp at 1.3GHz.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume48
Publication statusPublished - 2005
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2005 Feb 62005 Feb 10

Other

Other2005 IEEE International Solid-State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period05/2/605/2/10

Fingerprint

Clocks
Jitter
Dynamic frequency scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Kim, J. H., Kwak, Y. H., Yoon, S. R., Kim, M. Y., Kim, S-W., & Kim, C. (2005). A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 48). [28.4]

A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling. / Kim, Jin Han; Kwak, Young Ho; Yoon, Seok Ryung; Kim, Moo Young; Kim, Soo-Won; Kim, Chulwoo.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 48 2005. 28.4.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, JH, Kwak, YH, Yoon, SR, Kim, MY, Kim, S-W & Kim, C 2005, A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 48, 28.4, 2005 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 05/2/6.
Kim JH, Kwak YH, Yoon SR, Kim MY, Kim S-W, Kim C. A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 48. 2005. 28.4
Kim, Jin Han ; Kwak, Young Ho ; Yoon, Seok Ryung ; Kim, Moo Young ; Kim, Soo-Won ; Kim, Chulwoo. / A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 48 2005.
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