A CMOS DLL-based 120MHz to1.8GHz clock generator for dynamic frequency scaling

Jin Han Kim, Young Ho Kwak, Seok Ryung Yoon, Moo Young Kim, Soo Won Kim, Chulwoo Kim

Research output: Contribution to journalConference article

Abstract

A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6pspp at 1.3GHz.

Original languageEnglish
Article number28.4
Pages (from-to)428-429+718
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume48
Publication statusPublished - 2005
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2005 Feb 62005 Feb 10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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