A DLL-based clock generator for dynamic frequency scaling is fabricated in a 0.35μm CMOS technology. It generates clock signals ranging from 120MHz to 1.8GHz. The frequency can be dynamically changed. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. The proposed clock generator has a jitter of ±6.6pspp at 1.3GHz.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 2005|
|Event||2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States|
Duration: 2005 Feb 6 → 2005 Feb 10
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering