A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method

Gihoon Jung, Kyungrak Choi, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Coordinate Rotational Digital Computer (CORDIC) has been widely used as an iterative algorithm for performing rotations in many digital signal processing (DSP) applications. The CORDIC algorithm is divided into two modes, which are the rotation and vectoring modes. The conventional hardware architecture of CORDIC algorithm has two problems. First, though the computations of both modes are very similar, two separate modules are used in separate hardware architecture. Second, after computations of the whole iterations, an extra scaling operation to make a normalized output has been another computational burden. In this paper, we present a compact multi-mode CORDIC architecture, where both of the rotation and vectoring modes can be performed using a shared hardware architecture. In addition, Global-Shifting-Sum (GSS) approach which uses one adder and one barrel shifter is also proposed to efficiently eliminate the scaling operation of CORDIC. The proposed multi-mode GSS CORDIC is implemented as the iterative cross-folded architecture to minimize the area of CORDIC. The experimental results with 65nm CMOS process show 42% area reduction compared to the conventional two separate hardware architectures of CORDIC with minor degradation in accuracy.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages180-183
Number of pages4
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16/10/2516/10/28

Fingerprint

Digital computers
Computer hardware
Hardware
Computer architecture
Adders
Digital signal processing
Degradation

Keywords

  • CORDIC
  • cross-folded architecture
  • Global Shifting-Sum (GSS)
  • multi-mode
  • rotation mode
  • vectoring mode

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing

Cite this

Jung, G., Choi, K., & Park, J. (2017). A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 180-183). [7803927] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7803927

A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. / Jung, Gihoon; Choi, Kyungrak; Park, Jongsun.

2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 180-183 7803927.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jung, G, Choi, K & Park, J 2017, A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7803927, Institute of Electrical and Electronics Engineers Inc., pp. 180-183, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 16/10/25. https://doi.org/10.1109/APCCAS.2016.7803927
Jung G, Choi K, Park J. A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 180-183. 7803927 https://doi.org/10.1109/APCCAS.2016.7803927
Jung, Gihoon ; Choi, Kyungrak ; Park, Jongsun. / A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 180-183
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