A continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface (DDI)

This paper presents a continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface. This technique uses bottom hold circuit; to detect the incoming clock attenuation. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in 0.18-μm CMOS technology. Simulation results summarize that eye-width of minimum 0.75UI is achieved until -33dB channel loss at 1.65 (3bps. The average power consumption of the equalizer is 3.42 mW per channel, a very low value in comparison to those of previous researches, and the effective area is 0.127 mm².