A continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface (DDI)

Kyu Young Kim, Jae Tack Yoo, Soo-Won Kim

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents a continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface. This technique uses bottom hold circuit; to detect the incoming clock attenuation. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in 0.18-μm CMOS technology. Simulation results summarize that eye-width of minimum 0.75UI is achieved until -33dB channel loss at 1.65 (3bps. The average power consumption of the equalizer is 3.42 mW per channel, a very low value in comparison to those of previous researches, and the effective area is 0.127 mm2.

Original languageEnglish
Pages (from-to)638-643
Number of pages6
JournalIEICE Electronics Express
Volume4
Issue number21
DOIs
Publication statusPublished - 2007 Nov 10

Fingerprint

Equalizers
clocks
Clocks
attenuation
Display devices
CMOS
Electric power utilization
filters
Networks (circuits)
simulation

Keywords

  • Channel loss tracking
  • Continuous-time equalizer

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

Cite this

A continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface (DDI). / Kim, Kyu Young; Yoo, Jae Tack; Kim, Soo-Won.

In: IEICE Electronics Express, Vol. 4, No. 21, 10.11.2007, p. 638-643.

Research output: Contribution to journalArticle

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