A D-Band CMOS Amplifier with a New Dual-Frequency Interstage Matching Technique

Dong Hyun Kim, Doyoon Kim, Jae-Sung Rieh

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

A new interstage matching technique has been proposed and successfully applied to a {D}-band amplifier in a 65-nm CMOS technology. The proposed technique is based on a simultaneous conjugate matching at the interstages of multistage amplifiers at two frequencies, resulting in an increased bandwidth. The six-stage amplifier designed based on this technique shows a peak gain of 13.8 dB at 113.7 GHz with a 3-dB bandwidth of 11.2 GHz (110.6-121.8 GHz) without balun loss compensation, while consuming a dc power of 40 mW. Measured noise figure shows a minimum value of 10.8 dB at 115 GHz. The output P1 dB and the saturation output power Psat are-14 and-3 dBm, respectively. The circuit occupies an area of 1100 × 550μm2.

Original languageEnglish
Article number7845708
Pages (from-to)1580-1588
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Volume65
Issue number5
DOIs
Publication statusPublished - 2017 May 1

Fingerprint

CMOS
amplifiers
Bandwidth
Noise figure
bandwidth
output
Networks (circuits)
saturation
Compensation and Redress

Keywords

  • Amplifier
  • millimeter-wave circuits
  • wideband

ASJC Scopus subject areas

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

A D-Band CMOS Amplifier with a New Dual-Frequency Interstage Matching Technique. / Kim, Dong Hyun; Kim, Doyoon; Rieh, Jae-Sung.

In: IEEE Transactions on Microwave Theory and Techniques, Vol. 65, No. 5, 7845708, 01.05.2017, p. 1580-1588.

Research output: Contribution to journalArticle

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