A D-band multiplier-based OOK transceiver with supplementary transistor modeling in 65-nm bulk CMOS technology

Bohee Suh, Hyunkyu Lee, Sooyeon Kim, Sanggeun Jeon

Research output: Contribution to journalArticle


A D-band on-off keying (OOK) transceiver chipset is fabricated in a 65-nm bulk CMOS technology as a low-cost and highly integrative solution to short-distance wireless connectivity. Supplementary transistor modeling is performed for accurate circuit design at mm-wave frequencies. To overcome low transistor fmax and reduce dc power consumption, the transmitter employs a frequency-multiplier-based architecture with no power amplifier. The receiver adopts a non-coherent architecture consisting of a dc-coupled three-stage differential amplifier and an envelope detector. The OOK transmitter exhibits a measured output power of -9.8 dBm and an on-off level difference of 13.2 dB at 134.1 GHz. The receiver shows a measured average responsivity of 4.1 kV/W and a noise equivalent power of 211.4 pW/Hz1/2 over all D-band frequencies. The dc power consumption of the transmitter and the receiver is 76 and 32.5 mW, respectively. The transceiver is tested in both on-chip loopback and air-channel configurations and demonstrates data transmission up to 10 and 2 Gb/s at a distance of 0.03 m, respectively.

Original languageEnglish
Article number8603724
Pages (from-to)7783-7793
Number of pages11
JournalIEEE Access
Publication statusPublished - 2019 Jan 1



  • D-band
  • low-cost bulk CMOS
  • OOK
  • transceiver
  • transistor modeling
  • wireless communication

ASJC Scopus subject areas

  • Computer Science(all)
  • Materials Science(all)
  • Engineering(all)

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