This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-μm CMOS process. The implemented DVS circuit provides a supply voltage from 1.4V to 1.8V and the DFS circuit dynamically generates the system clock from 7.5MHz to 120MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm2 and 0.27 mm2 active areas, respectively.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 2008|
|Event||IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States|
Duration: 2008 Sep 21 → 2008 Sep 24
ASJC Scopus subject areas
- Electrical and Electronic Engineering