A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor

Sunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, Chulwoo Kim

Research output: Contribution to journalConference article

7 Citations (Scopus)

Abstract

This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-μm CMOS process. The implemented DVS circuit provides a supply voltage from 1.4V to 1.8V and the DFS circuit dynamically generates the system clock from 7.5MHz to 120MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm2 and 0.27 mm2 active areas, respectively.

Original languageEnglish
Article number4672144
Pages (from-to)551-554
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
Publication statusPublished - 2008
EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
Duration: 2008 Sep 212008 Sep 24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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