A digital LDO regulator with a self-clocking burst logic for ultralow power applications

Seong Jin Yun, Jiseong Lee, Yun Chan Im, Yong Sin Kim

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

Conventional capless digital low-dropout (DLDO) regulators adopt either a high-speed clock or the burst mode at the expense of a larger quiescent current in order to overcome the degradation of the load transient response caused by the absence of an external capacitor, which causes high power consumption. In this paper, a capless DLDO regulator with a self-clocking burst logic for ultralow power applications is proposed. The self-generated clock in the burst mode of the proposed burst logic is activated temporally in order to achieve both faster load transient response and lower quiescent current. The proposed DLDO regulator is implemented in 14-nm FinFET CMOS technology. The quiescent current and figure-of-merit (FoM) of the proposed DLDO regulator are 0.69 μA and 0.097 ps, respectively, with an active area of 0.0035 mm2, excluding a 0.1-nF integrated output capacitor.

Original languageEnglish
Article number8746678
Pages (from-to)2237-2245
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number10
DOIs
Publication statusPublished - 2019 Oct

Keywords

  • Burst mode
  • digital low-dropout (DLDO) regulator
  • low quiescent current
  • self-generated temporal clock

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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