A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition

In Chul Hwang, Sang Hun Song, Soo-Won Kim

Research output: Contribution to journalArticle

43 Citations (Scopus)

Abstract

A digitally controlled phase-locked loop (DCPLL) that achieves fast acquisition by employing a digital phase-frequency detector (DPFD) and a variable loop gain scheme was developed for an advanced clock synthesizer and was fabricated in a 3.3-V 0.6-μm CMOS process. The DPFD was developed to measure the frequency difference and to generate digital outputs corresponding to the difference. Using these features, the DCPLL achieves ideally one-cycle frequency acquisition when programmed with an appropriate gain. The experimental results show that the fabricated DCPLL exhibits three-cycle and one-cycle frequency acquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCO at 400 MHz), respectively.

Original languageEnglish
Pages (from-to)1574-1581
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume36
Issue number10
DOIs
Publication statusPublished - 2001 Oct 1

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Phase locked loops
Variable frequency oscillators
Detectors
Clocks

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition. / Hwang, In Chul; Song, Sang Hun; Kim, Soo-Won.

In: IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, 01.10.2001, p. 1574-1581.

Research output: Contribution to journalArticle

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