A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

I. Hwang, S. Lee, S. Lee, S. Kim

Research output: Contribution to journalConference article

26 Citations (Scopus)

Abstract

A digitally controlled phase-locked loop (DCPLL) with fast locking scheme for clock synthesis applications was synthesized. It reduced acquisition time by utilizing a digital frequency-difference detector (DFDD). The prototype chip had 136 picoseconds peak to peak jitter and 14.52ps root mean square (RMS) jitter at a frequency of 400 MHz.

Original languageEnglish
Pages (from-to)168-169
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2000
Event2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC - San Francisco, CA, United States
Duration: 2000 Feb 72000 Feb 9

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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