A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

I. Hwang; S. Lee; S. Lee; S. Kim

A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

I. Hwang, S. Lee, S. Lee, S. Kim

* Honorary professors

Research output: Contribution to journal › Conference article › peer-review

27 Citations (Scopus)

Abstract

A digitally controlled phase-locked loop (DCPLL) with fast locking scheme for clock synthesis applications was synthesized. It reduced acquisition time by utilizing a digital frequency-difference detector (DFDD). The prototype chip had 136 picoseconds peak to peak jitter and 14.52ps root mean square (RMS) jitter at a frequency of 400 MHz.

Original language	English
Pages (from-to)	168-169
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication status	Published - 2000
Event	2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC - San Francisco, CA, United States Duration: 2000 Feb 7 → 2000 Feb 9

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application",

abstract = "A digitally controlled phase-locked loop (DCPLL) with fast locking scheme for clock synthesis applications was synthesized. It reduced acquisition time by utilizing a digital frequency-difference detector (DFDD). The prototype chip had 136 picoseconds peak to peak jitter and 14.52ps root mean square (RMS) jitter at a frequency of 400 MHz.",

author = "I. Hwang and S. Lee and S. Lee and S. Kim",

year = "2000",

language = "English",

pages = "168--169",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC ; Conference date: 07-02-2000 Through 09-02-2000",

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TY - JOUR

T1 - A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

AU - Hwang, I.

AU - Lee, S.

AU - Kim, S.

PY - 2000

Y1 - 2000

N2 - A digitally controlled phase-locked loop (DCPLL) with fast locking scheme for clock synthesis applications was synthesized. It reduced acquisition time by utilizing a digital frequency-difference detector (DFDD). The prototype chip had 136 picoseconds peak to peak jitter and 14.52ps root mean square (RMS) jitter at a frequency of 400 MHz.

AB - A digitally controlled phase-locked loop (DCPLL) with fast locking scheme for clock synthesis applications was synthesized. It reduced acquisition time by utilizing a digital frequency-difference detector (DFDD). The prototype chip had 136 picoseconds peak to peak jitter and 14.52ps root mean square (RMS) jitter at a frequency of 400 MHz.

UR - http://www.scopus.com/inward/record.url?scp=0034428308&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034428308

SN - 0193-6530

SP - 168

EP - 169

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC

Y2 - 7 February 2000 through 9 February 2000

ER -

A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

Abstract

ASJC Scopus subject areas

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