A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

I. Hwang, S. Lee, S. Lee, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Citations (Scopus)

Abstract

A digitally controlled phase-locked loop (DCPLL) with fast locking scheme for clock synthesis applications was synthesized. It reduced acquisition time by utilizing a digital frequency-difference detector (DFDD). The prototype chip had 136 picoseconds peak to peak jitter and 14.52ps root mean square (RMS) jitter at a frequency of 400 MHz.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages168-169
Number of pages2
Publication statusPublished - 2000
Event2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC - San Francisco, CA, United States
Duration: 2000 Feb 72000 Feb 9

Other

Other2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC
CountryUnited States
CitySan Francisco, CA
Period00/2/700/2/9

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hwang, I., Lee, S., Lee, S., & Kim, S-W. (2000). A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 168-169)