In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR) to transfer four data in one clock cycle. In recent graphic memories, QDR is being implemented by a phase-locked loop (PLL). However, it is hard to apply a PLL to main and mobile memories for its high power dissipation and hardware cost. Therefore, we propose a new delay-locked loop-based quadrature clock generator (DLL-QCG) to replace a PLL. A sub-range technique is adopted for a phase interpolator (PI) to achieve a very fine resolution with low power and small area. A tiny resolution mitigates the jitter accumulation effect of the conventional all-digital DLL-QCG and reduces a phase error. With the introduction of the sub-range PI, the delay line structure is changed from two-stage (coarse-fine) to three-stage (coarse-fine-finer). To control this, we also develop a new controller, which ensures clock quality through seamless boundary switching at the fine-to-finer. The circuit is fabricated using a 28 nm CMOS FDSOI technology with a 1 V supply voltage and an area of 0.0072 mm2. It operates from 1.8 to 2.5 GHz and achieves a phase error of 3.35° to 6.35° without a quadrature-phase collector. In addition, the measured RMS and peak-to-peak jitters at operating bandwidth are 1.05 to 1.71 ps and 8.4 to 12 ps, respectively.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2020 Nov|
- multi-phase clock generator
- phase interpolator
ASJC Scopus subject areas
- Electrical and Electronic Engineering