A dual-gate cell (DGC) FeRAM with NDRO and random access scheme for nanoscale and terabit non-volatile memory

Hee B. Kang, Jae J. Lee, Suk Kyoung Hong, Jin Hong Ahn, Joong S. Kih, Man Young Sung, Young Kwon Sung

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL_1 to WL_m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read access. The write cycle composed with two sub-write cycles of data '1 preserve or data '0 write cycle after the first sub-write cycle of data '1 write to all active cells. The data '1 is preserved by the same voltage polarity between WL_1 and channel voltage of the MFSFET. The random access operation is possible in both read and write mode with non-destructive read out (NDRO).

Original languageEnglish
Title of host publicationIntegrated Ferroelectrics
Pages141-148
Number of pages8
Volume81
Edition1
DOIs
Publication statusPublished - 2006 Nov 1

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Keywords

  • Depletion DGC
  • Dual-gate cell (DGC) FeRAM
  • Enhancement DGC
  • MFSFET
  • Non-destructive read out (NDRO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Physics and Astronomy (miscellaneous)
  • Condensed Matter Physics

Cite this

Kang, H. B., Lee, J. J., Hong, S. K., Ahn, J. H., Kih, J. S., Sung, M. Y., & Sung, Y. K. (2006). A dual-gate cell (DGC) FeRAM with NDRO and random access scheme for nanoscale and terabit non-volatile memory. In Integrated Ferroelectrics (1 ed., Vol. 81, pp. 141-148) https://doi.org/10.1080/10584580600660249