A floorprint-based defect tolerance for nano-scale application-specific IC

A floorprint-based yield modeling, assurance and optimization method for the defect tolerant NASIC system under broken nanowire (NW) defects has been proposed in a short version of this paper, and the proposed models and methods are further validated and demonstrated through extensive parametric simulations in this paper. A yield model for each defect tolerant NASIC technique is developed based on the nature of the defects of concern in a floorprint-based analysis, thereby establishing an adequate foundation to evaluate and optimize the manufacturing process and defect tolerance by providing a capability to take into account the effect of each individual defect tolerance technique or synergetic effect of various combinations of the techniques on the overall expected yield of the product. According to the simulation results given in this paper, the defect tolerant NASIC system with 15 row and column NWs, respectively, each with length = 0.000034 on horizontal and vertical core nanoarray in a nanotile can achieve a yield higher than 99.8%. Ultimately, intelligent exploitation of the proposed yield modeling and simulation methods will make possible to realize a reliable NASIC-based computing system.