A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology

Se Chun Park, Seung Baek Park, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this study, a fully integrated Phase-locked loop (PLL) that is applicable to Universal Flash Storage (UFS) systems is presented. The fully integrated PLL is realized using a MOS capacitor as an on-chip loop filter (LF). To compensate for leakage current in the LF, a leakage current compensation scheme is presented. With the leakage compensation scheme, the peak-to-peak jitter and rms jitter are 40ps and 7.62ps, respectively. The area of the LF was reduced by around a sixteenth part compared with a metal insulator metal (MIM) capacitor.

Original languageEnglish
Title of host publication2015 IEEE International Conference on Consumer Electronics, ICCE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages587-588
Number of pages2
ISBN (Print)9781479975426
DOIs
Publication statusPublished - 2015 Mar 23
Event2015 IEEE International Conference on Consumer Electronics, ICCE 2015 - Las Vegas, United States
Duration: 2015 Jan 92015 Jan 12

Other

Other2015 IEEE International Conference on Consumer Electronics, ICCE 2015
CountryUnited States
CityLas Vegas
Period15/1/915/1/12

Keywords

  • Fully integrated PLL
  • Leakage compensation
  • Leakage current
  • MOS capacitor
  • Phase-locked loops
  • UFS

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

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  • Cite this

    Park, S. C., Park, S. B., & Kim, S-W. (2015). A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology. In 2015 IEEE International Conference on Consumer Electronics, ICCE 2015 (pp. 587-588). [7066538] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE.2015.7066538