A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time

Young Ho Kwak; Inhwa Jung; Chulwoo Kim

doi:10.1109/TCSII.2009.2038631

A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time

Young Ho Kwak, Inhwa Jung, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article

19 Citations (Scopus)

Abstract

This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

Original language	English
Article number	5420307
Pages (from-to)	120-125
Number of pages	6
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	57
Issue number	2
DOIs	https://doi.org/10.1109/TCSII.2009.2038631
Publication status	Published - 2010 Feb

Keywords

Electromagnetic interference (EMI)
Fast compensation
Low power
Process, voltage, and temperature (PVT) variation detection
Slew rate

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2009.2038631

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abstract = "This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.",

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AB - This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

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