A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time

Young Ho Kwak; Inhwa Jung; Chulwoo Kim

doi:10.1109/TCSII.2009.2038631

A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time

Young Ho Kwak, Inhwa Jung, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

22 Citations (Scopus)

Abstract

This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

Original language	English
Article number	5420307
Pages (from-to)	120-125
Number of pages	6
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	57
Issue number	2
DOIs	https://doi.org/10.1109/TCSII.2009.2038631
Publication status	Published - 2010 Feb

Keywords

Electromagnetic interference (EMI)
Fast compensation
Low power
Process, voltage, and temperature (PVT) variation detection
Slew rate

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2009.2038631

Cite this

@article{85a46d21d240465c9cffcfc369bb3074,

title = "A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time",

abstract = "This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.",

keywords = "Electromagnetic interference (EMI), Fast compensation, Low power, Process, voltage, and temperature (PVT) variation detection, Slew rate",

author = "Kwak, {Young Ho} and Inhwa Jung and Chulwoo Kim",

note = "Funding Information: Manuscript received July 24, 2009; revised October 27, 2009. Current version published February 26, 2010. This work was supported in part by Hynix Semiconductor Inc. and in part by the Korea Science and Engineering Foundation Grant R0A-2007-000-20059-0 funded by the Korea government (Ministry of Education, Science and Technology). The chip was fabricated through the MPW of IC Design Education Center (IDEC) supported by the Korea Ministry of Knowledge Economy (MKE). This paper was recommended by Associate Editor P. K. Hanumolu.",

year = "2010",

month = feb,

doi = "10.1109/TCSII.2009.2038631",

language = "English",

volume = "57",

pages = "120--125",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time

AU - Kwak, Young Ho

AU - Jung, Inhwa

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received July 24, 2009; revised October 27, 2009. Current version published February 26, 2010. This work was supported in part by Hynix Semiconductor Inc. and in part by the Korea Science and Engineering Foundation Grant R0A-2007-000-20059-0 funded by the Korea government (Ministry of Education, Science and Technology). The chip was fabricated through the MPW of IC Design Education Center (IDEC) supported by the Korea Ministry of Knowledge Economy (MKE). This paper was recommended by Associate Editor P. K. Hanumolu.

PY - 2010/2

Y1 - 2010/2

N2 - This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

AB - This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

KW - Electromagnetic interference (EMI)

KW - Fast compensation

KW - Low power

KW - Process, voltage, and temperature (PVT) variation detection

KW - Slew rate

UR - http://www.scopus.com/inward/record.url?scp=77649283880&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2009.2038631

DO - 10.1109/TCSII.2009.2038631

M3 - Article

AN - SCOPUS:77649283880

VL - 57

SP - 120

EP - 125

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 2

M1 - 5420307

ER -

A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time

Abstract

Keywords

ASJC Scopus subject areas

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