Abstract
This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.
| Original language | English |
|---|---|
| Article number | 5420307 |
| Pages (from-to) | 120-125 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 57 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2010 Feb 1 |
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Keywords
- Electromagnetic interference (EMI)
- Fast compensation
- Low power
- Process, voltage, and temperature (PVT) variation detection
- Slew rate
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time. / Kwak, Young Ho; Jung, Inhwa; Kim, Chulwoo.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 2, 5420307, 01.02.2010, p. 120-125.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time
AU - Kwak, Young Ho
AU - Jung, Inhwa
AU - Kim, Chulwoo
PY - 2010/2/1
Y1 - 2010/2/1
N2 - This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.
AB - This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18- μm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.13.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.
KW - Electromagnetic interference (EMI)
KW - Fast compensation
KW - Low power
KW - Process, voltage, and temperature (PVT) variation detection
KW - Slew rate
UR - http://www.scopus.com/inward/record.url?scp=77649283880&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77649283880&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2009.2038631
DO - 10.1109/TCSII.2009.2038631
M3 - Article
AN - SCOPUS:77649283880
VL - 57
SP - 120
EP - 125
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 2
M1 - 5420307
ER -