Abstract
The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub-block sections. The sub_block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub_block intervals. When one of four sub_blocks is activated, the two MSLs located at the edge of four sub_blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is about less than 50 mV. The average sensing voltage with 2Pr value of 5 μC/cm 2 and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 μC/cm 2.
| Original language | English |
|---|---|
| Title of host publication | Integrated Ferroelectrics |
| Pages | 245-254 |
| Number of pages | 10 |
| Volume | 67 |
| DOIs | |
| Publication status | Published - 2004 |
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Keywords
- Graded sense-load
- Hierarchical bitline
- Main-bitline
- Sub-bitline
- Sub_block
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Physics and Astronomy (miscellaneous)
- Condensed Matter Physics
- Electronic, Optical and Magnetic Materials
Cite this
A graded sense-load scheme and cell data distribution in FeRAM. / Kang, Hee Bok; Kim, In Soo; Lee, Jae Jin; Ahn, Jin Hong; Sung, Man Young; Sung, Young Kwon.
Integrated Ferroelectrics. Vol. 67 2004. p. 245-254.Research output: Chapter in Book/Report/Conference proceeding › Chapter
}
TY - CHAP
T1 - A graded sense-load scheme and cell data distribution in FeRAM
AU - Kang, Hee Bok
AU - Kim, In Soo
AU - Lee, Jae Jin
AU - Ahn, Jin Hong
AU - Sung, Man Young
AU - Sung, Young Kwon
PY - 2004
Y1 - 2004
N2 - The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub-block sections. The sub_block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub_block intervals. When one of four sub_blocks is activated, the two MSLs located at the edge of four sub_blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is about less than 50 mV. The average sensing voltage with 2Pr value of 5 μC/cm 2 and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 μC/cm 2.
AB - The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub-block sections. The sub_block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub_block intervals. When one of four sub_blocks is activated, the two MSLs located at the edge of four sub_blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is about less than 50 mV. The average sensing voltage with 2Pr value of 5 μC/cm 2 and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 μC/cm 2.
KW - Graded sense-load
KW - Hierarchical bitline
KW - Main-bitline
KW - Sub-bitline
KW - Sub_block
UR - http://www.scopus.com/inward/record.url?scp=33751186362&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33751186362&partnerID=8YFLogxK
U2 - 10.1080/10584580490899316
DO - 10.1080/10584580490899316
M3 - Chapter
AN - SCOPUS:33751186362
VL - 67
SP - 245
EP - 254
BT - Integrated Ferroelectrics
ER -