A graded sense-load scheme and cell data distribution in FeRAM

Hee Bok Kang, In Soo Kim, Jae Jin Lee, Jin Hong Ahn, Man Young Sung, Young Kwon Sung

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub-block sections. The sub_block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub_block intervals. When one of four sub_blocks is activated, the two MSLs located at the edge of four sub_blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is about less than 50 mV. The average sensing voltage with 2Pr value of 5 μC/cm 2 and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 μC/cm 2.

Original languageEnglish
Title of host publicationIntegrated Ferroelectrics
Pages245-254
Number of pages10
Volume67
DOIs
Publication statusPublished - 2004

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Keywords

  • Graded sense-load
  • Hierarchical bitline
  • Main-bitline
  • Sub-bitline
  • Sub_block

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

Cite this

Kang, H. B., Kim, I. S., Lee, J. J., Ahn, J. H., Sung, M. Y., & Sung, Y. K. (2004). A graded sense-load scheme and cell data distribution in FeRAM. In Integrated Ferroelectrics (Vol. 67, pp. 245-254) https://doi.org/10.1080/10584580490899316