Abstract
An artificial neural network algorithm is implemented using a low-cost field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. In this work, the training of the network is performed in the off-line computing environment and the results of the training are configured to the hardware in order to minimize the latency of the neural computation. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decisions on a set of input patterns in 11 clock cycles, or less than 200 ns with a 60 MHz clock. The result from the hardware neural computation is well predictable based on the off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experiments.
| Original language | English |
|---|---|
| Pages (from-to) | 816-820 |
| Number of pages | 5 |
| Journal | Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment |
| Volume | 581 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2007 Nov 1 |
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Keywords
- Artificial neural network
- FPGA
- Level 1 trigger
- VHDL
ASJC Scopus subject areas
- Instrumentation
- Nuclear and High Energy Physics
Cite this
A hardware implementation of artificial neural networks using field programmable gate arrays. / Won, Eunil.
In: Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 581, No. 3, 01.11.2007, p. 816-820.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A hardware implementation of artificial neural networks using field programmable gate arrays
AU - Won, Eunil
PY - 2007/11/1
Y1 - 2007/11/1
N2 - An artificial neural network algorithm is implemented using a low-cost field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. In this work, the training of the network is performed in the off-line computing environment and the results of the training are configured to the hardware in order to minimize the latency of the neural computation. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decisions on a set of input patterns in 11 clock cycles, or less than 200 ns with a 60 MHz clock. The result from the hardware neural computation is well predictable based on the off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experiments.
AB - An artificial neural network algorithm is implemented using a low-cost field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. In this work, the training of the network is performed in the off-line computing environment and the results of the training are configured to the hardware in order to minimize the latency of the neural computation. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decisions on a set of input patterns in 11 clock cycles, or less than 200 ns with a 60 MHz clock. The result from the hardware neural computation is well predictable based on the off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experiments.
KW - Artificial neural network
KW - FPGA
KW - Level 1 trigger
KW - VHDL
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UR - http://www.scopus.com/inward/citedby.url?scp=35348832307&partnerID=8YFLogxK
U2 - 10.1016/j.nima.2007.08.163
DO - 10.1016/j.nima.2007.08.163
M3 - Article
AN - SCOPUS:35348832307
VL - 581
SP - 816
EP - 820
JO - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
JF - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
SN - 0168-9002
IS - 3
ER -