A high speed low-power accumulator for direct digital frequency synthesizer

Yong Sin Kim, Sung Mo Kang

Research output: Contribution to journalConference article

10 Citations (Scopus)

Abstract

A high speed low-power 32-bit accumulator for direct digital frequency synthesizer (DDFS) is presented. The DDFS consists of a phase accumulator, a phase-to-sine amplitude converter, and a D/A converter. For accumulator design, high speed pipelining scheme is commonly used to increase throughput and to reduce power consumption. Our design decreases power consumption and the number of registers down to 24% and 37% of the conventional pipelined accumulator.

Original languageEnglish
Article number4014944
Pages (from-to)502-505
Number of pages4
JournalIEEE MTT-S International Microwave Symposium Digest
DOIs
Publication statusPublished - 2006
Event2006 IEEE MTT-S International Microwave Symposium Digest - San Francisco, CA, United States
Duration: 2006 Jun 112006 Jun 16

Keywords

  • Accumulator
  • Direct digital frequency synthesizer (DDFS)
  • Gated clock
  • Low power
  • Pipelining

ASJC Scopus subject areas

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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