A hybrid multimode BCH encoder architecture for area efficient re-encoding approach

Hoyoung Tang, Gihoon Jung, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used as a denominator of remainder operator for re-encoding. In the proposed approach, several minimal polynomials are employed as the denominators of remainder operators by utilizing the hardware of hybrid multimode BCH encoder. As a result, the minimum input length for SC can be employed for SC implementation through reencoding scheme, which leads to considerable area and latency reduction in SC module design. The proposed BCH encoder architecture and reduced SC modules are implemented using Samsung 65nm technology. The experimental results show that, in case of BCH (8640, 8192, 32) codes, the total area of SC modules are reduced by 96% compared to the previous re-encoding based SC module design, while the proposed multimode BCH encoder architecture also provides the reconfigurable error correction capability for 1 ≤ tsel ≤ 32.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1997-2000
Number of pages4
Volume2015-July
ISBN (Print)9781479983919
DOIs
Publication statusPublished - 2015 Jul 27
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: 2015 May 242015 May 27

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period15/5/2415/5/27

Fingerprint

Mathematical operators
Polynomials
Error correction
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tang, H., Jung, G., & Park, J. (2015). A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 1997-2000). [7169067] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169067

A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. / Tang, Hoyoung; Jung, Gihoon; Park, Jongsun.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 1997-2000 7169067.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tang, H, Jung, G & Park, J 2015, A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 2015-July, 7169067, Institute of Electrical and Electronics Engineers Inc., pp. 1997-2000, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 15/5/24. https://doi.org/10.1109/ISCAS.2015.7169067
Tang H, Jung G, Park J. A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1997-2000. 7169067 https://doi.org/10.1109/ISCAS.2015.7169067
Tang, Hoyoung ; Jung, Gihoon ; Park, Jongsun. / A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1997-2000
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