Abstract
This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used as a denominator of remainder operator for re-encoding. In the proposed approach, several minimal polynomials are employed as the denominators of remainder operators by utilizing the hardware of hybrid multimode BCH encoder. As a result, the minimum input length for SC can be employed for SC implementation through reencoding scheme, which leads to considerable area and latency reduction in SC module design. The proposed BCH encoder architecture and reduced SC modules are implemented using Samsung 65nm technology. The experimental results show that, in case of BCH (8640, 8192, 32) codes, the total area of SC modules are reduced by 96% compared to the previous re-encoding based SC module design, while the proposed multimode BCH encoder architecture also provides the reconfigurable error correction capability for 1 ≤ tsel ≤ 32.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1997-2000 |
| Number of pages | 4 |
| Volume | 2015-July |
| ISBN (Print) | 9781479983919 |
| DOIs | |
| Publication status | Published - 2015 Jul 27 |
| Event | IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 2015 May 24 → 2015 May 27 |
Other
| Other | IEEE International Symposium on Circuits and Systems, ISCAS 2015 |
|---|---|
| Country | Portugal |
| City | Lisbon |
| Period | 15/5/24 → 15/5/27 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. / Tang, Hoyoung; Jung, Gihoon; Park, Jongsun.
Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 1997-2000 7169067.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A hybrid multimode BCH encoder architecture for area efficient re-encoding approach
AU - Tang, Hoyoung
AU - Jung, Gihoon
AU - Park, Jongsun
PY - 2015/7/27
Y1 - 2015/7/27
N2 - This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used as a denominator of remainder operator for re-encoding. In the proposed approach, several minimal polynomials are employed as the denominators of remainder operators by utilizing the hardware of hybrid multimode BCH encoder. As a result, the minimum input length for SC can be employed for SC implementation through reencoding scheme, which leads to considerable area and latency reduction in SC module design. The proposed BCH encoder architecture and reduced SC modules are implemented using Samsung 65nm technology. The experimental results show that, in case of BCH (8640, 8192, 32) codes, the total area of SC modules are reduced by 96% compared to the previous re-encoding based SC module design, while the proposed multimode BCH encoder architecture also provides the reconfigurable error correction capability for 1 ≤ tsel ≤ 32.
AB - This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used as a denominator of remainder operator for re-encoding. In the proposed approach, several minimal polynomials are employed as the denominators of remainder operators by utilizing the hardware of hybrid multimode BCH encoder. As a result, the minimum input length for SC can be employed for SC implementation through reencoding scheme, which leads to considerable area and latency reduction in SC module design. The proposed BCH encoder architecture and reduced SC modules are implemented using Samsung 65nm technology. The experimental results show that, in case of BCH (8640, 8192, 32) codes, the total area of SC modules are reduced by 96% compared to the previous re-encoding based SC module design, while the proposed multimode BCH encoder architecture also provides the reconfigurable error correction capability for 1 ≤ tsel ≤ 32.
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U2 - 10.1109/ISCAS.2015.7169067
DO - 10.1109/ISCAS.2015.7169067
M3 - Conference contribution
AN - SCOPUS:84946231973
SN - 9781479983919
VL - 2015-July
SP - 1997
EP - 2000
BT - Proceedings - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
ER -