@inproceedings{26a28c6d28694601a5468fb135362e9c,
title = "A Last-Level Cache Management for Enhancing Endurance of Phase Change Memory",
abstract = "Since PCM memory has various advantages over DRAM, it is attracting attention as the next-generation memory. However, because of a few drawbacks, such as long write latency and limited write endurance, PCM cannot be used as the conventional system's main memory. This paper proposes the last-level cache (LLC) management algorithm to improve PCM's lifetime by evicting dirty blocks evenly to the PCM. As a result, we achieved 35% longer lifetime improvement without any PCM modification. ",
keywords = "LLC, PCM, Wear-leveling, bit-counter",
author = "Lee, {Won Jun} and Kim, {Chang Hyun} and Kim, {Seon Wook}",
note = "Funding Information: This work was supported in part by SK Hynix Inc. Publisher Copyright: {\textcopyright} 2021 IEEE.; 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 ; Conference date: 27-06-2021 Through 30-06-2021",
year = "2021",
month = jun,
day = "27",
doi = "10.1109/ITC-CSCC52171.2021.9501266",
language = "English",
series = "2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021",
}