Abstract
This paper presents a QRS detector operating in multi-mode with low complexity, power saving consumption for Implantable Pacemaker IC. The complexity of detector is optimized after testing dynamic range of internal signals. Correspondingly, static power consumption is reduced significantly. The dynamic power consumption is saved by using down-sampling rate structure and turning off deactive filter banks bases on noise estimation. This QRS detector is evaluated with MIT-BIH Arrhythmia database archives >99% detection ratio. A soft IP core is prototyped on FPGA and synthesized by Samsung 0.18um standard library.
| Original language | English |
|---|---|
| Title of host publication | 2006 IEEE International Systems-on-Chip Conference, SOC |
| Pages | 160-163 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2007 Dec 1 |
| Event | 2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States Duration: 2006 Sep 24 → 2006 Sep 27 |
Other
| Other | 2006 IEEE International Systems-on-Chip Conference, SOC |
|---|---|
| Country | United States |
| City | Austin, TX |
| Period | 06/9/24 → 06/9/27 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A low complexity, low power, programmable QRS detector based on wavelet transform for Implantable Pacemaker IC. / Hoang, Thanh Tung; Son, Jong Pil; Kang, Yu Ri; Kim, Chae Ryung; Chung, Hae Young; Kim, Soo-Won.
2006 IEEE International Systems-on-Chip Conference, SOC. 2007. p. 160-163 4063041.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A low complexity, low power, programmable QRS detector based on wavelet transform for Implantable Pacemaker IC
AU - Hoang, Thanh Tung
AU - Son, Jong Pil
AU - Kang, Yu Ri
AU - Kim, Chae Ryung
AU - Chung, Hae Young
AU - Kim, Soo-Won
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper presents a QRS detector operating in multi-mode with low complexity, power saving consumption for Implantable Pacemaker IC. The complexity of detector is optimized after testing dynamic range of internal signals. Correspondingly, static power consumption is reduced significantly. The dynamic power consumption is saved by using down-sampling rate structure and turning off deactive filter banks bases on noise estimation. This QRS detector is evaluated with MIT-BIH Arrhythmia database archives >99% detection ratio. A soft IP core is prototyped on FPGA and synthesized by Samsung 0.18um standard library.
AB - This paper presents a QRS detector operating in multi-mode with low complexity, power saving consumption for Implantable Pacemaker IC. The complexity of detector is optimized after testing dynamic range of internal signals. Correspondingly, static power consumption is reduced significantly. The dynamic power consumption is saved by using down-sampling rate structure and turning off deactive filter banks bases on noise estimation. This QRS detector is evaluated with MIT-BIH Arrhythmia database archives >99% detection ratio. A soft IP core is prototyped on FPGA and synthesized by Samsung 0.18um standard library.
UR - http://www.scopus.com/inward/record.url?scp=43749084806&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=43749084806&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2006.283872
DO - 10.1109/SOCC.2006.283872
M3 - Conference contribution
AN - SCOPUS:43749084806
SN - 0780397819
SN - 9780780397811
SP - 160
EP - 163
BT - 2006 IEEE International Systems-on-Chip Conference, SOC
ER -