A low complexity reconfigurable DCT architecture to trade off image quality for power consumption

Jongsun Park, Kaushik Roy

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.

Original languageEnglish
Pages (from-to)399-410
Number of pages12
JournalJournal of Signal Processing Systems
Volume53
Issue number3
DOIs
Publication statusPublished - 2008 Dec 1

Fingerprint

Discrete Cosine Transform
Discrete cosine transforms
Image Quality
Low Complexity
Image quality
Power Consumption
Electric power utilization
Trade-offs
Computational complexity
Computational Complexity
Power Saving
Cross product
Scalar, inner or dot product
Architecture
Reuse
Degradation

Keywords

  • Discrete cosine transform
  • Low computational complexity
  • Low power VLSI design

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Signal Processing
  • Theoretical Computer Science
  • Control and Systems Engineering
  • Modelling and Simulation

Cite this

A low complexity reconfigurable DCT architecture to trade off image quality for power consumption. / Park, Jongsun; Roy, Kaushik.

In: Journal of Signal Processing Systems, Vol. 53, No. 3, 01.12.2008, p. 399-410.

Research output: Contribution to journalArticle

@article{cc9ece0266294bd9a7470055081928ea,
title = "A low complexity reconfigurable DCT architecture to trade off image quality for power consumption",
abstract = "In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38{\%} of area and 18{\%} of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28{\%} to 56{\%} for 3 different trade-off levels.",
keywords = "Discrete cosine transform, Low computational complexity, Low power VLSI design",
author = "Jongsun Park and Kaushik Roy",
year = "2008",
month = "12",
day = "1",
doi = "10.1007/s11265-008-0242-2",
language = "English",
volume = "53",
pages = "399--410",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer New York",
number = "3",

}

TY - JOUR

T1 - A low complexity reconfigurable DCT architecture to trade off image quality for power consumption

AU - Park, Jongsun

AU - Roy, Kaushik

PY - 2008/12/1

Y1 - 2008/12/1

N2 - In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.

AB - In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.

KW - Discrete cosine transform

KW - Low computational complexity

KW - Low power VLSI design

UR - http://www.scopus.com/inward/record.url?scp=53649106962&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=53649106962&partnerID=8YFLogxK

U2 - 10.1007/s11265-008-0242-2

DO - 10.1007/s11265-008-0242-2

M3 - Article

AN - SCOPUS:53649106962

VL - 53

SP - 399

EP - 410

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 3

ER -