A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time

Moo Young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A portable multiphase clock generator, independent of input duty ratio, has been developed. The proposed open-loop and full-digital architecture has a fast lock time of two clock cycles and is a simple, robust and portable IP. In addition, the complementary delay line is implemented to achieve high phase resolution at a wide frequency range. The generator has been implemented in a 0.18um CMOS process and operates at variable input frequencies ranging from 800MHz to 1.6GHz.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages369-372
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
DOIs
Publication statusPublished - 2007
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: 2007 Sep 162007 Sep 19

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period07/9/1607/9/19

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Kim, M. Y., Shin, D., Chae, H., Ok, S., & Kim, C. (2007). A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 369-372). [4405754] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405754