A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver

Dongyeob Shin, Jongsun Park

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substituting the square roots and divisions with coordinate rotation digital computer (CORDIC) operations. In the proposed architecture, when implementing the division by the results of square root, the key design point is that the rotation directions of CORDIC are shared between vectoring and rotation modes using the orthogonality of the CORDIC rotation matrix. As a result, the division operation can be performed with the assistance of square root, leading to the hardware cost reduction. The overhead of scaling factor compensation has also been reduced with pre-scaling. The proposed low complexity scheme can be implemented in the semipipelined and iterative architectures for high throughput and small area applications, respectively. Hardware implementation results with 65-nm CMOS process show that the proposed semipipelined architecture achieves 17% and 141% improvement of normalized hardware efficiency in QRD and projection operations, respectively, compared with the conventional approaches.

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
Publication statusAccepted/In press - 2018 Jan 29

Fingerprint

MIMO systems
Decomposition
Digital computers
Hardware
Computer operating procedures
Cost reduction
Throughput

Keywords

  • Complexity theory
  • Computer architecture
  • CORDIC
  • energy efficiency
  • Gram-Schmidt
  • Hardware
  • hardware efficiency.
  • Matrix decomposition
  • MIMO
  • MIMO communication
  • QR decomposition
  • Receiving antennas

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

@article{d14777af4bf14fdfbb39a8e6bb199525,
title = "A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver",
abstract = "Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substituting the square roots and divisions with coordinate rotation digital computer (CORDIC) operations. In the proposed architecture, when implementing the division by the results of square root, the key design point is that the rotation directions of CORDIC are shared between vectoring and rotation modes using the orthogonality of the CORDIC rotation matrix. As a result, the division operation can be performed with the assistance of square root, leading to the hardware cost reduction. The overhead of scaling factor compensation has also been reduced with pre-scaling. The proposed low complexity scheme can be implemented in the semipipelined and iterative architectures for high throughput and small area applications, respectively. Hardware implementation results with 65-nm CMOS process show that the proposed semipipelined architecture achieves 17{\%} and 141{\%} improvement of normalized hardware efficiency in QRD and projection operations, respectively, compared with the conventional approaches.",
keywords = "Complexity theory, Computer architecture, CORDIC, energy efficiency, Gram-Schmidt, Hardware, hardware efficiency., Matrix decomposition, MIMO, MIMO communication, QR decomposition, Receiving antennas",
author = "Dongyeob Shin and Jongsun Park",
year = "2018",
month = "1",
day = "29",
doi = "10.1109/TCSI.2018.2795342",
language = "English",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver

AU - Shin, Dongyeob

AU - Park, Jongsun

PY - 2018/1/29

Y1 - 2018/1/29

N2 - Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substituting the square roots and divisions with coordinate rotation digital computer (CORDIC) operations. In the proposed architecture, when implementing the division by the results of square root, the key design point is that the rotation directions of CORDIC are shared between vectoring and rotation modes using the orthogonality of the CORDIC rotation matrix. As a result, the division operation can be performed with the assistance of square root, leading to the hardware cost reduction. The overhead of scaling factor compensation has also been reduced with pre-scaling. The proposed low complexity scheme can be implemented in the semipipelined and iterative architectures for high throughput and small area applications, respectively. Hardware implementation results with 65-nm CMOS process show that the proposed semipipelined architecture achieves 17% and 141% improvement of normalized hardware efficiency in QRD and projection operations, respectively, compared with the conventional approaches.

AB - Despite a low algorithmic complexity, Gram-Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substituting the square roots and divisions with coordinate rotation digital computer (CORDIC) operations. In the proposed architecture, when implementing the division by the results of square root, the key design point is that the rotation directions of CORDIC are shared between vectoring and rotation modes using the orthogonality of the CORDIC rotation matrix. As a result, the division operation can be performed with the assistance of square root, leading to the hardware cost reduction. The overhead of scaling factor compensation has also been reduced with pre-scaling. The proposed low complexity scheme can be implemented in the semipipelined and iterative architectures for high throughput and small area applications, respectively. Hardware implementation results with 65-nm CMOS process show that the proposed semipipelined architecture achieves 17% and 141% improvement of normalized hardware efficiency in QRD and projection operations, respectively, compared with the conventional approaches.

KW - Complexity theory

KW - Computer architecture

KW - CORDIC

KW - energy efficiency

KW - Gram-Schmidt

KW - Hardware

KW - hardware efficiency.

KW - Matrix decomposition

KW - MIMO

KW - MIMO communication

KW - QR decomposition

KW - Receiving antennas

UR - http://www.scopus.com/inward/record.url?scp=85041410472&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85041410472&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2018.2795342

DO - 10.1109/TCSI.2018.2795342

M3 - Article

AN - SCOPUS:85041410472

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

ER -