A low power all-digital PLL with power optimized digitally controlled oscillator

Doo Chan Lee, Kyu Young Kim, Young Jae Min, Kyung Min Kim, Ammar Abdullah, Jongsun Park, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm CMOS process. Chip measurement results show that the total circuit occupies 0.083mm2 area, and the DCO power dissipation was optimized to 2.83mW at the output frequency of 600MHz. The power optimized DCO is implemented in ADPLL and save the overall power dissipation of ADPLL.

Original languageEnglish
Title of host publication2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 - Hong Kong, China
Duration: 2010 Dec 152010 Dec 17

Publication series

Name2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

Other

Other2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
CountryChina
CityHong Kong
Period10/12/1510/12/17

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Lee, D. C., Kim, K. Y., Min, Y. J., Kim, K. M., Abdullah, A., Park, J., & Kim, S. W. (2010). A low power all-digital PLL with power optimized digitally controlled oscillator. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 [5713739] (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). https://doi.org/10.1109/EDSSC.2010.5713739