A low power all-digital PLL with power optimized digitally controlled oscillator

Doo Chan Lee; Kyu Young Kim; Young Jae Min; Kyung Min Kim; Ammar Abdullah; Jongsun Park; Soo Won Kim

doi:10.1109/EDSSC.2010.5713739

A low power all-digital PLL with power optimized digitally controlled oscillator

Doo Chan Lee, Kyu Young Kim, Young Jae Min, Kyung Min Kim, Ammar Abdullah, Jongsun Park, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm CMOS process. Chip measurement results show that the total circuit occupies 0.083mm² area, and the DCO power dissipation was optimized to 2.83mW at the output frequency of 600MHz. The power optimized DCO is implemented in ADPLL and save the overall power dissipation of ADPLL.

Original language	English
Title of host publication	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
DOIs	https://doi.org/10.1109/EDSSC.2010.5713739
Publication status	Published - 2010
Event	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 - Hong Kong, China Duration: 2010 Dec 15 → 2010 Dec 17

Publication series

Name	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

Other

Other	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
Country/Territory	China
City	Hong Kong
Period	10/12/15 → 10/12/17

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2010.5713739

Cite this

Lee, D. C., Kim, K. Y., Min, Y. J., Kim, K. M., Abdullah, A., Park, J., & Kim, S. W. (2010). A low power all-digital PLL with power optimized digitally controlled oscillator. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 [5713739] (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). https://doi.org/10.1109/EDSSC.2010.5713739

A low power all-digital PLL with power optimized digitally controlled oscillator. / Lee, Doo Chan; Kim, Kyu Young; Min, Young Jae et al.

2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. 2010. 5713739 (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, DC, Kim, KY, Min, YJ, Kim, KM, Abdullah, A, Park, J & Kim, SW 2010, A low power all-digital PLL with power optimized digitally controlled oscillator. in 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010., 5713739, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010, Hong Kong, China, 10/12/15. https://doi.org/10.1109/EDSSC.2010.5713739

Lee DC, Kim KY, Min YJ, Kim KM, Abdullah A, Park J et al. A low power all-digital PLL with power optimized digitally controlled oscillator. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. 2010. 5713739. (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). doi: 10.1109/EDSSC.2010.5713739

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title = "A low power all-digital PLL with power optimized digitally controlled oscillator",

abstract = "This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm CMOS process. Chip measurement results show that the total circuit occupies 0.083mm2 area, and the DCO power dissipation was optimized to 2.83mW at the output frequency of 600MHz. The power optimized DCO is implemented in ADPLL and save the overall power dissipation of ADPLL.",

author = "Lee, {Doo Chan} and Kim, {Kyu Young} and Min, {Young Jae} and Kim, {Kyung Min} and Ammar Abdullah and Jongsun Park and Kim, {Soo Won}",

note = "Copyright: Copyright 2011 Elsevier B.V., All rights reserved.; 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 ; Conference date: 15-12-2010 Through 17-12-2010",

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N2 - This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm CMOS process. Chip measurement results show that the total circuit occupies 0.083mm2 area, and the DCO power dissipation was optimized to 2.83mW at the output frequency of 600MHz. The power optimized DCO is implemented in ADPLL and save the overall power dissipation of ADPLL.

AB - This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm CMOS process. Chip measurement results show that the total circuit occupies 0.083mm2 area, and the DCO power dissipation was optimized to 2.83mW at the output frequency of 600MHz. The power optimized DCO is implemented in ADPLL and save the overall power dissipation of ADPLL.

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A low power all-digital PLL with power optimized digitally controlled oscillator

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