A low-power architecture for maximum a posteriori decoding

Marisa López-Vallejo, Syed Aon Mujtaba, Inkyu Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper we present a novel architecture for soft-input soft-output (SISO) Maximum a Posteriori (MAP) decoding. The architecture leverages an ASIP (Application Specific Instruction-Set Processor) structure, where the datapath has been designed to achieve high-speed performance and low power dissipation. Salient features of this architecture include: (a) delayed renormalization of the a metrics with register by-passing to reduce latency, (b) use of register files to minimize power dissipation, and (c) microprogrammed control to achieve flexibility. The resulting architecture for the SISO-MAP decoder achieves a maximum throughput of 10.9 Msymbols/second, operating at 142 MHz and dissipating 21 mW in the datapath.

Original languageEnglish
Title of host publicationConference Record of the Asilomar Conference on Signals, Systems and Computers
EditorsM.B. Matthews
Pages47-51
Number of pages5
Volume1
Publication statusPublished - 2002
EventThe Thirty-Sixth Asilomar Conference on Signals Systems and Computers - Pacific Groove, CA, United States
Duration: 2002 Nov 32002 Nov 6

Other

OtherThe Thirty-Sixth Asilomar Conference on Signals Systems and Computers
CountryUnited States
CityPacific Groove, CA
Period02/11/302/11/6

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Hardware and Architecture

Cite this

López-Vallejo, M., Mujtaba, S. A., & Lee, I. (2002). A low-power architecture for maximum a posteriori decoding. In M. B. Matthews (Ed.), Conference Record of the Asilomar Conference on Signals, Systems and Computers (Vol. 1, pp. 47-51)