As the pipeline length increases, the accuracy in a branch prediction gets critical to overall performance. In designing a branch predictor, in addition to accuracy, microarchitects should consider power consumption, especially in embedded processors. In this paper, we propose a low power branch predictor, which is based on the gshare predictor, by accessing the BTB (Branch Target Buffer) only when the prediction from the PHT (Prediction History Table) is taken. To enable this, the PHT is accessed one cycle earlier to prevent the additional delay. As a side effect, two predictions from the PHT are obtained at one access to the PHT, which leads to more power reduction. The proposed branch predictor reduces the power consumption, not requiring any additional storage arrays, not incurring additional delay (except just one MUX delay) and never harming accuracy. The simulation results show that the proposed predictor reduces the power consumption by 43-52%.
|Number of pages||11|
|Journal||Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|
|Publication status||Published - 2004 Dec 1|
ASJC Scopus subject areas
- Computer Science(all)
- Biochemistry, Genetics and Molecular Biology(all)
- Theoretical Computer Science