A low-power cache with successive tag comparison algorithm

Tae Chan Kim, Chulwoo Kim, Bong Young Chung, Soo-Won Kim

Research output: Contribution to journalArticle

Abstract

In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (central processor unit), MCU (micro controller unit), cache, et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.

Original languageEnglish
Pages (from-to)227-230
Number of pages4
JournalCurrent Applied Physics
Volume5
Issue number3
DOIs
Publication statusPublished - 2005 Mar 1

Fingerprint

Electric power utilization
controllers
Controllers
very large scale integration
central processing units
simulation

Keywords

  • Cache
  • Low power consumption
  • Successive tag algorithm

ASJC Scopus subject areas

  • Materials Science (miscellaneous)
  • Condensed Matter Physics
  • Surfaces and Interfaces

Cite this

A low-power cache with successive tag comparison algorithm. / Kim, Tae Chan; Kim, Chulwoo; Chung, Bong Young; Kim, Soo-Won.

In: Current Applied Physics, Vol. 5, No. 3, 01.03.2005, p. 227-230.

Research output: Contribution to journalArticle

Kim, Tae Chan ; Kim, Chulwoo ; Chung, Bong Young ; Kim, Soo-Won. / A low-power cache with successive tag comparison algorithm. In: Current Applied Physics. 2005 ; Vol. 5, No. 3. pp. 227-230.
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