A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array

Hoonki Kim; Young Jae Min; Yonghwan Kim; Soowon Kim

doi:10.1109/EDSSC.2008.4760721

A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array

Hoonki Kim, Young Jae Min, Yonghwan Kim, Soowon Kim

* Honorary professors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

30 Citations (Scopus)

Abstract

A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18μm standard CMOS technology. This ADC has signal to noise and distortion ratios (SNDR) of 53.8dB for 1.5V supply voltage. It consumes 13.4μW at sampling rates of 137kS/s.

Original language	English
Title of host publication	2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
DOIs	https://doi.org/10.1109/EDSSC.2008.4760721
Publication status	Published - 2008
Event	2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC - Hong Kong, China Duration: 2008 Dec 8 → 2008 Dec 10

Publication series

Name	2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC

Other

Other	2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
Country/Territory	China
City	Hong Kong
Period	08/12/8 → 08/12/10

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2008.4760721

Cite this

A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array. / Kim, Hoonki; Min, Young Jae; Kim, Yonghwan et al.

2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC. 2008. 4760721 (2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, H, Min, YJ, Kim, Y & Kim, S 2008, A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array. in 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC., 4760721, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, Hong Kong, China, 08/12/8. https://doi.org/10.1109/EDSSC.2008.4760721

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abstract = "A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18μm standard CMOS technology. This ADC has signal to noise and distortion ratios (SNDR) of 53.8dB for 1.5V supply voltage. It consumes 13.4μW at sampling rates of 137kS/s.",

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AB - A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18μm standard CMOS technology. This ADC has signal to noise and distortion ratios (SNDR) of 53.8dB for 1.5V supply voltage. It consumes 13.4μW at sampling rates of 137kS/s.

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T3 - 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC

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A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array

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