A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array

Hoonki Kim, Young Jae Min, Yonghwan Kim, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Citations (Scopus)

Abstract

A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18μm standard CMOS technology. This ADC has signal to noise and distortion ratios (SNDR) of 53.8dB for 1.5V supply voltage. It consumes 13.4μW at sampling rates of 137kS/s.

Original languageEnglish
Title of host publication2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC - Hong Kong, China
Duration: 2008 Dec 82008 Dec 10

Other

Other2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
CountryChina
CityHong Kong
Period08/12/808/12/10

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kim, H., Min, Y. J., Kim, Y., & Kim, S-W. (2008). A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array. In 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC [4760721] https://doi.org/10.1109/EDSSC.2008.4760721