A Low-power network-on-chip architecture for tile-based chip multi-processors

Anastasios Psarras, Junghee Lee, Pavlos Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)


Technology scaling of tiled-based CMPs reduces the physical size of each tile and increases the number of tiles per die. This trend directly impacts the on-chip interconnect; even though the tile population increases, the inter-tile link distances scale down proportionally to the tile dimensions. The decreasing inter-tile wire lengths can be exploited to enable swift link traversal between neighboring tiles, after appropriate wire engineering. Building on this premise, we propose a technique to rapidly transfer flits between adjacent routers in half a clock cycle, by utilizing both edges of the clock during the sending and receiving operations. Half-cycle link traversal enables, for the first time, substantial reductions in (a) link power, irrespective of the data switching profile, and (b) buffer power (through buffer-size reduction), without incurring any latency/throughput loss. In fact, the proposed architecture also yields some latency improvements over a baseline NoC. Detailed hardware analysis using placed-and-routed designs, and cycle-accurate full-system simulations corroborate the significant power and latency improvements.

Original languageEnglish
Title of host publicationGLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Number of pages6
ISBN (Electronic)9781450342742
Publication statusPublished - 2016 May 18
Externally publishedYes
Event26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 - Boston, United States
Duration: 2016 May 182016 May 20

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Conference26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016
CountryUnited States

ASJC Scopus subject areas

  • Engineering(all)

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