A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX

A power reduction scheme that uses AC termination at RX and a TX output driver with an active inductor part (AIP) is proposed for a point-to-point post-LPDDR4 interface at 8 Gb/s. AC termination at the receiver I/O can reduce the power consumption by preventing DC power loss. However, this causes inter symbol interference (ISI), owing to the difference in gain depending on the frequency. Thus, AC termination generates more jitter, which results in a smaller eye-opening than the conventional on-die termination (ODT). The AIP in the TX output driver reduces the low-frequency gain and the ISI caused by the AC termination. This reduces the jitter and improves the eye-opening. The proposed AIP allows to change the frequency range by adjusting the resistance (RAI), capacitance (CAI), and the size of the MOSFET according to the resistance (Rac) and capacitance (Cac) used in the AC termination at the RX. In this paper, the AC termination at the RX and the AIP in the TX were implemented in a 28-nm CMOS process and operated at 8 Gb/s with a 3 inch FR4 microstrip line including a board, and a socket model. The proposed transceiver chip achieves a peak-to-peak jitter of 43.6 ps and power reduction of 31% compared with chips without AC termination and AIP.