A low-power programmable DLL-based clock generator with wide-range antiharmonic lock

Jabeom Koo, Sunghwa Ok, Chulwoo Kim

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

Original languageEnglish
Pages (from-to)21-25
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume56
Issue number1
DOIs
Publication statusPublished - 2009 Feb 12

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Clocks
Electric power utilization

Keywords

  • Antiharmonic lock
  • Frequency multiplier

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A low-power programmable DLL-based clock generator with wide-range antiharmonic lock. / Koo, Jabeom; Ok, Sunghwa; Kim, Chulwoo.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 1, 12.02.2009, p. 21-25.

Research output: Contribution to journalArticle

@article{72667eaf2670473898dbf85dd413c405,
title = "A low-power programmable DLL-based clock generator with wide-range antiharmonic lock",
abstract = "A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.",
keywords = "Antiharmonic lock, Frequency multiplier",
author = "Jabeom Koo and Sunghwa Ok and Chulwoo Kim",
year = "2009",
month = "2",
day = "12",
doi = "10.1109/TCSII.2008.2008531",
language = "English",
volume = "56",
pages = "21--25",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - A low-power programmable DLL-based clock generator with wide-range antiharmonic lock

AU - Koo, Jabeom

AU - Ok, Sunghwa

AU - Kim, Chulwoo

PY - 2009/2/12

Y1 - 2009/2/12

N2 - A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

AB - A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-μm CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

KW - Antiharmonic lock

KW - Frequency multiplier

UR - http://www.scopus.com/inward/record.url?scp=59649114991&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=59649114991&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2008.2008531

DO - 10.1109/TCSII.2008.2008531

M3 - Article

AN - SCOPUS:59649114991

VL - 56

SP - 21

EP - 25

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 1

ER -